This invention relates to microcomputers, and more particularly, to microprocessors and digital signal processors that use multiple DMA controllers.
Direct Memory Access (DMA) controllers are well-known devices used, for example, to transfer data between a microcomputer""s primary memory and associated peripheral devices (see, e.g., Michael Slater, Microprocessor-Based Design, Prentice-Hall, 1989, pp. 273-280). These devices are often used to support data transfer from primary memory to peripheral devices requiring high data transfer rates (for example, graphics display terminals, digital to analog converters and disk drives). In managing data transfer between a microcomputer processing unit""s primary memory and such devices, DMA controllers can often allow higher rates of data transfer (higher bandwidth) than would be achieved by the processing unit in such transfers, and increase the time available to the processing unit to support other tasks.
Microcomputer applications for DMA controllers are increasing in number. For example, an increasing number of functions formerly performed by integrated circuit general processing units executing stored program instructions are currently being implemented as distinct, dedicated hardware devices or device elements. To minimize interaction between the general processing units and these dedicated hardware elements, DMA controllers are typically used to move data between the hardware elements and the primary memory.
In support of some microcomputer operations, a common set of data may be processed by more than one hardware element. One example of this can be found in systems supporting Internet Packet Security (IPSEC). IPSEC systems incorporate, for example, two dedicated hardware elements: 1) hash message authentication code (HMAC) and 2) encryption/decryption. The order in which these two elements are invoked depends on the security regime defined by the data packet that is being processed. For example, a first packet may require decryption followed by HMAC, while a second packet may require HMAC followed by decryption. Because each element requires an original copy of each data packet, each packet must be transferred to each of the two hardware elements.
To support data transfer to multiple hardware elements, current microcomputers often incorporate multiple DMA controllers, each independently supporting one associated hardware element. While these individual controllers provide high data transfer rates for their hardware elements, in the course of operation they will each independently read and write common data. As a result, system throughput may be adversely impacted when a large volume of common data is being transferred to these hardware elements.
Throughput is substantially improved in a microcomputer system employing multiple, co-dependent DMA controllers to manage data transfers associated with dedicated hardware functions. Each system includes a main processing unit, a memory, at least two DMA controllers, and at least two peripheral devices implementing dedicated hardware functions. Each of these elements is interconnected via a global data bus. In addition, the main processing unit, the memory and the DMA controllers are interconnected via a global control bus and a global address bus. Further, each DMA controller is interconnected to an associated peripheral device via a local address bus and a local control bus, and is able to communicate with the other DMA controllers through a DMA communications bus.
An exemplary embodiment of the invention includes two co-dependent DMA controllers each interconnected to a peripheral device. Each DMA controller provides the signals over its local control bus and local address bus for data to be written to its associated peripheral device. However, only one DMA controller is designated to read data from memory and then write this data to each of the peripheral devices. In this manner, the separate read and write commands executed by DMA controllers in prior art systems to transfer common data to multiple peripheral devices are reduced to a single set of read and write commands by a DMA controller xe2x80x9cleaderxe2x80x9d, thereby reducing bus resources required for such data transfers.